As semiconductor devices have become highly integrated, about 70 nm may be a critical dimension. Next-generation semiconductor devices having critical dimensions below about 70 nm present difficulties to conventional manufacturing techniques, such as mis-operation due to non-uniformity of a number of electrons, resistance-capacitance (RC) delay, a leakage current over a permissible value due to a tunneling effect of a gate insulation layer, mis-operation due to thermal and quantum mechanical vibrations.
In order to overcome the above-mentioned problems, developing a new method of manufacturing a semiconductor device based on different phenomena and principles compared to present techniques is needed.
When a particle has a nanometer-scale size, physical properties of the particle follows quantum mechanics instead of classical mechanics, and therefore the particle has characteristics such as electron tunneling in a quantum well, a characteristic of electrons that are restricted to a low dimension, a wave property of electrons, etc.
Hereinafter, the problems occurring according as the semiconductor device becomes highly integrated will be illustrated in detail.
A common non-volatile semiconductor device includes a floating gate electrode capable of inputting and outputting charges between a tunnel oxide layer and a control oxide layer. A thickness of the floating gate electrode included in a non-volatile semiconductor device has to be thinner as a critical dimension of gate structures of the non-volatile semiconductor device becomes thinner. For example, when the critical dimension of the gate structures is about 90 nm, the thickness of the floating gate electrode has to be about 8 nm. In addition, when the critical dimension of the gate structures is about 65 nm, the thickness of the floating gate electrode has to be about 6 nm. Moreover, when the critical dimension of the gate structures is about 45 nm, the thickness of the floating gate electrode has to be about 3 nm. However, when the thickness of the floating gate electrode is below about 6 nm, a leakage current of the floating gate electrode increases over a permissible value. Thus, charge cannot be stored in the floating gate electrode, and the non-volatile semiconductor device cannot function properly.
Nowadays, in order to overcome a scaling limit of non-volatile semiconductor devices, nanocrystalline materials are used as means for storing charge instead of the floating gate electrode.
In a non-volatile semiconductor device using nanocrystalline materials, charges are dispersedly trapped in hundreds of the nanocrystalline materials so that storing charge is not seriously affected even though several nanocrystalline materials have defects. Thus, a non-volatile semiconductor device using nanocrystalline materials can have a reduced leakage current so as to be highly integrated in comparison with a non-volatile semiconductor device including the floating gate electrode. Nanocrystalline silicon is primarily being researched as the nanocrystalline material.
As one method of forming nanocrystalline silicon, a common chemical vapor deposition (CVD) process can be used. However, in the CVD process, controlling deposition time and temperature is not easy; therefore, nanocrystalline silicon has difficulty in achieving proper particle sizes, a uniform distribution, and a uniform density. In addition, nanocrystalline silicon formed by the CVD process has a large step difference so that performing successive processes is difficult.
As another method of forming nanocrystalline silicon, after forming a silicon oxide layer having a high content of silicon, that is, a silicon-rich oxide layer, the nanocrystalline silicon in the silicon-rich oxide layer is extracted. For example, a process for forming the silicon-rich oxide layer includes a low-pressure CVD (LPCVD) process, a plasma-enhanced CVD (PECVD) process, an electron beam evaporation process, etc.
By the above-mentioned processes, however, a stoichiometrically stable silicon oxide layer can be easily formed, and in the stoichiometrically stable silicon oxide layer, nanocrystalline silicon is never extracted. Additionally, even though a non-stoichiometrical silicon oxide layer is formed by the processes, silicon content included in the silicon-rich oxide layer is not uniform so that forming a thin film including nanocrystalline silicon having proper particle sizes, a uniform distribution, and a uniform density is very difficult.
When nanocrystalline silicon does not have the proper particle sizes, the uniform distribution, and the uniform density, an amount of charge able to be stored in nanocrystalline silicon varies. Thus, a non-volatile semiconductor device including nanocrystalline silicon having the non-uniform particle sizes and distribution does not operate reproducibly.